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wide supply range, rail-to-rail output instrumentation amplifier preliminary technical data AD8426 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 2 channels in a small, 4 mm 4 mm lfcsp lfcsp package has no metal pad more routing room no current leakage to pad gain set with 1 external resistor gain range: 1 to 1000 input voltage goes below ground inputs protected beyond supplies very wide power supply range single supply: 2.2 v to 36 v dual supply: 1.35 v to 18 v bandwidth (g = 1): 1.5 mhz cmrr (g = 1): 80 db minimum input noise: 22 nv/hz typical supply current (per amp): 350 a specified temperature range: ?40c to +125c applications industrial process controls bridge amplifiers medical instrumentation portable data acquisition multichannel systems pin configuration 1 2 3 4 12 11 10 9 5678 13 14 15 16 ?in1 +in1 rg1 rg1 AD8426 +v s out1 out2 ?v s ?in2 +in2 rg2 rg2 09490-001 +v s ?v s ref1 ref2 figure 1. table 1. instrumentation amplifiers by category 1 general purpose zero drift military grade low power high speed pga ad8220 ad8231 ad620 ad627 ad8250 ad8221 ad8290 ad621 ad623 ad8251 ad8222 ad8293 ad524 ad8235 ad8253 ad8224 ad8553 ad526 ad8236 ad8228 ad8556 ad624 AD8426 ad8295 ad8557 ad8226 ad8227 1 see www.analog.com for the latest instrumentation amplifiers. general description the AD8426 is a dual channel, low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain from 1 to 1000. the AD8426 is designed to work with a variety of signal voltages. a wide input range and rail-to-rail output allow the signal to make full use of the supply rails. because the input range also includes the ability to go below the negative supply, small signals near ground can be amplified without requiring dual supplies. the AD8426 operates on supplies ranging from 1.35 v to 18 v for dual supplies and 2.2 v to 36 v for single supply. the robust AD8426 inputs are designed to connect to real- world sensors. in addition to its wide operating range, the AD8426 can handle voltages beyond the rails. for example, with a 5 v supply, the part is guaranteed to withstand 35 v at the input with no damage. minimum as well as maximum input bias currents are specified to facilitate open-wire detection. the AD8426 is designed to make pcb routing easy and efficient. the two amplifiers are arranged in a logical way so that typical application circuits have short routes and few vias. unlike most chip scale packages, the AD8426 does not have an exposed metal pad on the back of the part, which frees additional space for routing and vias. the AD8426 offers two in amps in the equivalent board space of a typical msop package. the AD8426 is ideal for multichannel, space-constrained industrial applications. unlike other low cost, low power instrumentation amplifiers, the AD8426 is designed with a minimum gain of 1 and can easily handle 10 v signals. with its space-saving lfcsp package and 125c temperature rating, the AD8426 thrives in tightly packed, zero airflow designs. the ad8226 is the single channel version of the AD8426 . www..net
AD8426 preliminary technical data rev. prd | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin configuration ............................................................................. 1 ? general description ......................................................................... 1 ? specifications ..................................................................................... 3 ? dual-supply operation ............................................................... 3 ? single-supply operation ............................................................. 5 ? absolute maximum ratings ............................................................ 8 ? thermal resistance ...................................................................... 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 11 ? architecture ................................................................................. 11 ? gain selection .............................................................................. 11 ? reference terminal ..................................................................... 11 ? input voltage range ................................................................... 12 ? layout .......................................................................................... 12 ? input bias current return path ............................................... 13 ? input protection ......................................................................... 13 ? radio frequency interference (rfi) ........................................ 14 ? applications information .............................................................. 15 ? differential drive ....................................................................... 15 ? precision strain gage ................................................................. 16 ? driving an adc.......................................................................... 16 ? outline dimensions ....................................................................... 17 ?
preliminary technical data AD8426 rev. prd | page 3 of 20 specifications dual-supply operation +v s = +15 v, ?v s = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, specifications referred to input, unless otherwise noted. table 2. test conditions/ comments a grade b grade parameter min typ max min typ max unit common-mode rejection ratio (cmrr) v cm = ?10 v to +10 v cmrr, dc to 60 hz g = 1 80 86 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db cmrr at 5 khz g = 1 80 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 100 100 db noise total noise: e n = (e ni 2 + (e no /g) 2 ) voltage noise f = 1 khz input voltage noise, e ni 22 24 22 24 nv/hz output voltage noise, e no 120 125 120 125 nv/hz rti noise f = 0.1 hz to 10 hz g = 1 2 2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.4 0.4 v p-p current noise f = 1 khz 100 100 fa/hz f = 0.1 hz to 10 hz 3 3 pa p-p voltage offset total offset voltage: v os = v osi + (v oso /g) input offset, v osi v s = 5 v to 15 v 300 150 v average temperature coefficient t a = ?40c to +125c 0.5 3 0.5 1.5 v/c output offset, v oso v s = 5 v to 15 v 1200 800 v average temperature coefficient t a = ?40c to +125c 2 12 1 8 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db input current input bias current 1 t a = +25c 5 20 27 5 20 27 na t a = +125c 5 15 25 5 15 25 na t a = ?40c 5 30 35 5 30 35 na average temperature coefficient t a = ?40c to +125c 70 70 pa/c input offset current t a = +25c 2 1 na t a = +125c 2 1 na
AD8426 preliminary technical data rev. prd | page 4 of 20 test conditions/ comments a grade b grade parameter min typ max min typ max unit t a = ?40c 3 1 na average temperature coefficient t a = ?40c to +125c 5 5 pa/c reference input r in 100 100 k i in 7 7 a voltage range ?v s +v s ?v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.01 % dynamic response small-signal ?3 db bandwidth g = 1 1500 1500 khz g = 10 160 160 khz g = 100 20 20 khz g = 1000 2 2 khz settling time 0.01% 10 v step g = 1 25 25 s g = 10 15 15 s g = 100 40 40 s g = 1000 350 350 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.05 0.02 % g = 5 to 1000 0.3 0.15 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 10 r l 2 k 10 10 ppm g = 100 r l 2 k 75 75 ppm g = 1000 r l 2 k 750 750 ppm gain vs. temperature 2 g = 1 t a = ?40c to +85c 10 2 ppm/c t a = +85c to +125c 10 5 ppm/c g > 1 t a = ?40c to +125c ?100 ?100 ppm/c input v s = 1.35 v to +36 v input impedance differential 0.8||2 0.8||2 g||pf common mode 0.4||2 0.4||2 g||pf input operating voltage range 3 t a = +25c ?v s ? 0.1 +v s ? 0.8 ?v s ? 0.1 +v s ? 0.8 v t a = +125c ?v s ? 0.05 +v s ? 0.6 ?v s ? 0.05 +v s ? 0.6 v t a = ?40c ?v s ? 0.15 +v s ? 0.9 ?v s ? 0.15 +v s ? 0.9 v input overvoltage range t a = ?40c to +125c +v s ? 40 ?v s + 40 +v s ? 40 ?v s + 40 v output output swing r l = 2 k to ground t a = +25c ?v s + 0.4 +v s ? 0.7 ?v s + 0.4 +v s ? 0.7 v t a = +125c ?v s + 0.4 +v s ? 1.0 ?v s + 0.4 +v s ? 1.0 v t a = ?40c ?v s + 1.2 +v s ? 1.1 ?v s + 1.2 +v s ? 1.1 v
preliminary technical data AD8426 rev. prd | page 5 of 20 test conditions/ comments a grade b grade parameter min typ max min typ max unit r l = 10 k to ground t a = +25c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v t a = +125c ?v s + 0.3 +v s ? 0.3 ?v s + 0.3 +v s ? 0.3 v t a = ?40c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v r l = 100 k to ground t a = ?40c to +125c ?v s + 0.1 +v s ? 0.1 ?v s + 0.1 +v s ? 0.1 v short-circuit current 13 13 ma power supply operating range dual-supply operation 1.35 18 1.35 18 v quiescent current (per amplifier) t a = +25c 350 425 350 425 a t a = ?40c 250 325 250 325 a t a = +85c 450 525 450 525 a t a = +125c 525 600 525 600 a temperature range ?40 +125 ?40 +125 c 1 the input stage uses pnp transi stors; therefore, input bias c urrent always flows into the part. 2 the values specified for g > 1 do not include the effects of the external gain-setting resistor, r g . 3 input voltage range of the AD8426 input stage. the input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage . see the input voltage range se ction for more information. single-supply operation +v s = 2.7 v, ?v s = 0 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, specifications referred to input, unless otherwise noted. table 3. test conditions/ comments a grade b grade parameter min typ max min typ max unit common-mode rejection ratio (cmrr) v cm = 0 v to 1.7 v cmrr, dc to 60 hz g = 1 80 86 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db cmrr at 5 khz g = 1 80 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 100 100 db noise total noise: e n = (e ni 2 + (e no /g) 2 ) voltage noise f = 1 khz input voltage noise, e ni 22 24 22 24 nv/hz output voltage noise, e no 120 125 120 125 nv/hz rti noise f = 0.1 hz to 10 hz g = 1 2 2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.4 0.4 v p-p current noise f = 1 khz 100 100 fa/hz f = 0.1 hz to 10 hz 3 3 pa p-p voltage offset total offset voltage: v os = v osi + (v oso /g) input offset, v osi 300 150 v
AD8426 preliminary technical data rev. prd | page 6 of 20 test conditions/ comments a grade b grade parameter min typ max min typ max unit average temperature coefficient t a = ?40c to +125c 0.5 3 0.5 1.5 v/c output offset, v oso 1200 800 v average temperature coefficient t a = ?40c to +125c 2 12 1 8 v/c offset rti vs. supply (psr) v s = 0 v to 1.7 v g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db input current input bias current 1 t a = +25c 5 20 27 5 20 27 na t a = +125c 5 15 25 5 15 25 na t a = ?40c 5 30 35 5 30 35 na average temperature coefficient t a = ?40c to +125c 70 70 pa/c input offset current t a = +25c 2 1 na t a = +125c 2 1 na t a = ?40c 3 1 na average temperature coefficient t a = ?40c to +125c 5 5 pa/c reference input r in 100 100 k i in 7 7 a voltage range ?v s +v s ?v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.01 % dynamic response small-signal ?3 db bandwidth g = 1 1500 1500 khz g = 10 160 160 khz g = 100 20 20 khz g = 1000 2 2 khz settling time 0.01% 2 v step g = 1 6 6 s g = 10 6 6 s g = 100 35 35 s g = 1000 350 350 s slew rate ? ? g = 1 ? 0.4 0.4 v/s g = 5 to 100 ? 0.6 0.6 v/s gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error g = 1 v out = 0.8 v to 1.8 v 0.04 0.01 % g = 5 to 1000 v out = 0.2 v to 2.5 v 0.3 0.1 % gain vs. temperature 2 g = 1 t a = ?40c to +85c 5 1 ppm/c t a = +85c to +125c 5 2 ppm/c g > 1 t a = ?40c to +125c ?100 -100 ppm/c
preliminary technical data AD8426 rev. prd | page 7 of 20 test conditions/ comments a grade b grade parameter min typ max min typ max unit input ?v s = 0 v, +v s = 2.7 v to 36 v input impedance differential 0.8||2 0.8||2 g||pf common mode 0.4||2 0.4||2 g||pf input operating voltage range 3 t a = +25c ?0.1 +v s ? 0.7 ?0.1 +v s ? 0.7 v t a = +125c ?0.05 +v s ? 0.6 ?0.05 +v s ? 0.6 v t a = ?40c ?0.15 +v s ? 0.9 ?0.15 +v s ? 0.9 v input overvoltage range t a = ?40c to +125c +v s ? 40 ?v s + 40 +v s ? 40 ?v s + 40 v output output swing r l = 10 k to 1.35 v t a = ?40c to +125c 0.1 +v s ? 0.1 0.1 +v s ? 0.1 v short-circuit current 13 13 ma power supply operating range single-supply operation 2.2 36 2.2 36 v quiescent current (per amplifier) ?v s = 0 v, +v s = 2.7 v t a = +25c 325 400 325 400 a t a = ?40c 250 325 250 325 a t a = +85c 425 500 425 500 a t a = +125c 475 550 475 550 a temperature range ?40 +125 ?40 +125 c 1 the input stage uses pnp transi stors; therefore, input bias c urrent always flows into the part. 2 the values specified for g > 1 do not include the effects of the external gain-setting resistor, r g . 3 input voltage range of the AD8426 input stage. the input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage . see the input voltage range se ction for more information.
AD8426 preliminary technical data rev. prd | page 8 of 20 absolute maximum ratings table 4. parameter rating supply voltage 18 v output short-circuit current indefinite maximum voltage at ?inx or +inx ?v s + 40 v minimum voltage at ?inx or +inx +v s ? 40 v refx voltage v s storage temperature range ?65c to +150c specified temperature range ?40c to +125c maximum junction temperature 130c esd human body model 1.5 kv charged device model 1.5 kv machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the ja value in table 5 assumes a 4-layer jedec standard board with zero airflow. table 5. package ja unit 16-lead lfcsp_vq 86 c/w esd caution
preliminary technical data AD8426 rev. prd | page 9 of 20 pin configuration and fu nction descriptions 1 2 3 4 12 11 10 9 5678 13 14 15 16 ?in1 +in1 rg1 rg1 AD8426 +v s out1 out2 ?v s ?in2 +in2 rg2 rg2 09490-002 +v s ?v s ref1 ref2 figure 2. pin configuration table 6. pin function description pin no. mnemonic description 1 ?in1 negative input, in-amp 1 2 rg1 gain-setting resistor terminal, in-amp 1 3 rg1 gain-setting resistor terminal, in-amp 1 4 +in1 positive input, in-amp 1 5 +vs positive supply 6 ref1 reference adjust, in-amp 1 7 ref2 reference adjust, in-amp 2 8 ?vs negative supply 9 +in2 positive input, in-amp 2 10 rg2 gain-setting resistor terminal, in-amp 2 11 rg2 gain-setting resistor terminal, in-amp 2 12 ?in2 negative input, in-amp 2 13 ?vs negative supply 14 out2 output, in-amp 2 15 out1 output, in-amp 1 16 +vs positive supply
AD8426 preliminary technical data rev. prd | page 10 of 20 typical performance characteristics t = 25c, v s = 15 v, r l = 10 k, unless otherwise noted. \ 1.00 \ 0.50 ? ? ? ? ? ? 0.50 1.00 1.50 2.00 2 . 5 0 0.00 \ input common-mode voltage (v) ?? +0.01, ? +1.90 ? +1.35, ? +1.95 +2.17, ? +0.90 +2.61, ? +0.37 +2.61, ? +1.13 +0.01, ? +0.31 +0.01, ? +1.28 +1.35, ?\ 0.41 0.00, ?\ 0.45 v = 1.35v ref ref v = 0v output voltage (v) figure 3. input common-mode voltage vs. output voltage, single supply, v s = 2.7 v, g = 1 5.00 ? ? 4.00 ? ? 3.00 2.00 ? ? 1.00 0.00 \ 1.00 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6 input common mode voltage (v) output voltage (v) +2.50, +4.25 +0.02, +4.25 +4.90, +3.03 +0.02, +2.95 +4.64, +2.03 +4.90, +0.82 +0.01, +0.87 +2.50, -0.40 +0.01, -0.30 v = 2.5v v = 0v ref ref figure 4. input common-mode voltage vs. output voltage, single supply, v s = 5 v, g = 1 ? ? ? ?\ 6.0 2.0 0 ?2.0 ?6.0 ?6.0 ?2.0 0 2.0 6.0 00000-000 input common mode voltage (v) output voltage (v) 4.0 ?4.0 ?4.0 4.0 0.0, +4.25 ?4.93, ?2.83 ?4.93, +1.77 +4.87, +1.79 +4.90, ?2.84 0.0, ?5.30 figure 5. input common-mode voltage vs. output voltage, dual supply, v s = 5 v, g = 1 20.0 15.0 0 ?15.0 ?20.0 ?20.0 ?15.0 0 15.0 20.0 00000-000 input common mode voltage (v) output voltage (v) 10.0 5.0 ?5.0 ?10.0 ?10.0 ?5.0 10.0 5.0 0.0, ?15.3 0.0, ?12.3 +11.8, ?6.5 +14.8, ?7.9 +14.8, +6.8 +11.9, +5.3 0.0, +14.2 0.0, +11.2 ?11.9, +5.2 ?14.9, +6.7 ?14.9, ?7.6 ?11.9, ?6.0 v = 12v s v = 15v s figure 6. input common-mode voltage vs. output voltage, dual supply, v s = 15 v, g = 1
preliminary technical data AD8426 rev. prd | page 11 of 20 theory of operation a3 r2 24.7k ? r1 24.7k ? a1 a2 q2 q1 ?in +in +v s ?v s r3 50k ? r4 50k ? r5 50k ? r b r b +v s ?v s v out ref node 1 node 2 r g v bias + v s ?v s +v s ?v s node 4 node 3 r6 50k ? difference amplifier stage gain stage esd and overvoltage protection esd and overvoltage protection ?v s 0 9490-003 figure 7. simplified schematic architecture the AD8426 is based on the classic three op amp topology. this topology has two stages: a gain stage (preamplifier) to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. figure 7 shows a simplified schematic of one of the instrumentation amplifiers in the AD8426 . the first stage works as follows: to maintain a constant voltage across the bias resistor, r b , a1 must keep node 3 at a constant diode drop above the positive input voltage. similarly, a2 keeps node 4 at a constant diode drop above the negative input voltage. therefore, a replica of the differential input voltage is placed across the gain setting resistor, r g . the current that flows across this resistance must also flow through the r1 and r2 resistors, creating a gained differential signal between the a2 and a1 out- puts. note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop up, is also still present. the second stage is a difference amplifier, composed of a3 and four 50 k resistors. the purpose of this stage is to remove the common-mode signal from the amplified differential signal. the transfer function of the AD8426 is v out = g ( v in+ ? v in? ) + v ref where: g r g k 49.4 1 ? ? gain selection placing a resistor across the r g terminals sets the gain of the AD8426 , which can be calculated by referring to table 7 or by using the following gain equation: 1 k 49.4 ? ? g r g table 7. gains achieved using 1% resistors 1% standard table value of r g calculated gain 49.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the AD8426 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resistor should be added to the AD8426 specifications to determine the total gain accu- racy of the system. when the gain resistor is not used, gain error and gain drift are minimal. reference terminal the output voltage of the AD8426 is developed with respect to the potential on the reference terminal. this is useful when the output signal needs to be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level- shift the output so that the AD8426 can drive a single-supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v. for the best performance, source impedance to the ref terminal should be kept below 2 . as shown in figure 8, the reference terminal, ref, is at one end of a 50 k resistor. additional impedance at the ref terminal adds to this 50 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be computed by 2 (50 k + r ref )/100 k + r ref .
AD8426 preliminary technical data rev. prd | page 12 of 20 only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades the cmrr of the amplifier. incor r ect AD8426 v ref cor r ect AD8426 op1177 + ? v ref cor r ect AD8426 AD8426 + ? v ref 09490-053 figure 8. driving the reference pin input voltage range the three op amp architecture of the AD8426 applies gain in the first stage before removing common-mode voltage in the difference amplifier stage. in addition, the input transistors in the first stage shift the common-mode voltage up one diode drop. therefore, internal nodes between the first and second stages (node 1 and node 2 in figure 7) experience a combina- tion of gained signal, common-mode signal, and a diode drop. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not. equation 1 to equation 3 can be used to understand how the gain (g), common-mode input voltage (v cm ), differential input voltage (v diff ), and reference voltage (v ref ) interact. the values for the constants, v ?limit , v +limit , and v ref_limit , at different temper- atures are shown in table 8. these three formulas, along with the input and output range specifications in table 2 and table 3, set the operating boundaries of the part. limit s diff cm v v g v v ? ? ? ? ? 2 ) )( ( (1) limit s diff cm v v g v v ? ? ? ? ? 2 ) )( ( (2) limit ref s ref cm diff v v v v g v _ 2 2 ) )( ( ? ? ? ? ? (3) table 8. input voltage range constants for various temperatures temperature v ?limit v +limit v ref_limit ?40c ?0.55 +0.8 +1.3 +25c ?0.35 +0.7 +1.15 +85c ?0.15 +0.65 +1.05 +125c ?0.05 +0.6 +0.9 the common-mode input voltage range shifts upward with temp- erature. at cold temperatures, the part requires extra headroom from the positive supply, whereas operation near the negative supply has more margin. conversely, at hot temperatures, the part requires less headroom from the positive supply but is subject to the worst-case conditions for input voltages near the negative supply. a typical part functions up to the boundaries described in this section. however, for best performance, designing with a few hundred millivolts extra margin is recommended. as signals approach the boundary, internal transistors begin to saturate, which can affect frequency and linearity performance. layout to ensure optimum performance of the AD8426 at the pcb level, care must be taken in the design of the board layout. the AD8426 pins are arranged in a logical manner to aid in this task. 1 2 3 4 12 11 10 9 5678 13 14 15 16 ?in1 +in1 rg1 rg1 AD8426 +v s out1 out2 ?v s ?in2 +in2 rg2 rg2 09490-002 +v s ?v s ref1 ref2 figure 9. pinout diagram package considerations the AD8426 is available in a 16-lead, 4 mm 4 mm lfcsp with no exposed paddle. the footprint from another 4 mm 4 mm lfcsp part should not be copied because it may not have the correct lead pitch and lead width dimensions. refer to the outline dimensions section for the correct dimensions. hidden paddle package the AD8426 is available in an lfcsp package with a hidden paddle. unlike chip scale packages where the pad limits routing capability, this package allows routes and vias directly beneath the chip, so that the full space savings of the small lfcsp can be realized. although the package has no metal in the center of the part, the manufacturing process leaves a very small section of exposed metal at each of the package corners, as shown in figure 10 and in figure 17 in the outline dimensions section. this metal is connected to ? v s through the part. because of the possibility of a short, vias should not be placed underneath these exposed metal tabs.
preliminary technical data AD8426 rev. prd | page 13 of 20 09490-055 hidden paddle bottom view exposed lead frame tabs notes 1. exposed lead frame tabs at the four corners of the package are internally connected to +v s . refer to the outline dimensions page, for further information on package availability. figure 10. hidden paddle package, bottom view common-mode rejection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to keep cmrr across frequency high, the input source impedance and capacitance of each path should be closely matched. additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins can also affect cmrr over frequency. if the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible. power supplies a stable dc voltage should be used to power the instrumenta- tion amplifier. noise on the supply pins can adversely affect performance. a 0.1 f capacitor should be placed as close as possible to each supply pin. as shown in figure 11, a 10 f capacitor can be used farther away from the part. in most cases, it can be shared by other precision integrated circuits. AD8426 + v s +in ?in load ref 0.1f 10f 0.1f 10f ?v s v out 09490-006 figure 11. supply decoupling, ref, and output referred to local ground references the output voltage of the AD8426 is developed with respect to the potential on the reference terminal. care should be taken to tie ref to the appropriate local ground. this should also help minimize crosstalk between the two channels. input bias current return path the input bias current of the AD8426 must have a return path to ground. when the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in figure 12. thermocouple +v s ref ?v s AD8426 capacitively coupled +v s ref c c ?v s AD8426 transformer +v s ref ?v s AD8426 incorrec t capacitively coupled +v s ref c r r c ?v s AD8426 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? AD8426 transformer +v s ref ?v s AD8426 correct 09490-007 figure 12. creating an inpu t bias current return path input protection the AD8426 has very robust inputs and typically does not need additional input protection. input voltages can be up to 40 v from the opposite supply rail. for example, with a +5 v positive supply and a ?8 v negative supply, the part can safely withstand voltages from ?35 v to +32 v. unlike some other instrumentation amplifiers, the part can handle large differen- tial input voltages even when the part is in high gain. the rest of the AD8426 terminals should be kept within the supplies. all terminals of the AD8426 are protected against esd.
AD8426 preliminary technical data rev. prd | page 14 of 20 limiting resistors and low leakage diode clamps such as the bav199, the fjh1100s, or the sp720 should be used. radio frequency interference (rfi) rf interference is often a problem when amplifiers are used in applications where there are strong rf signals. the precision circuits in the AD8426 can rectify the rf signals so that they appear as a dc offset voltage error. to avoid this rectification, place a low-pass rc filter at the input of the instrumentation amplifier (see figure 13). the filter limits both the differential and common-mode bandwidth, as shown in the following equations: ) 2 ( 2 1 c d diff c c r uency filterfreq ? ? c cm rc uency filterfreq 2 1 ? where c d ? 10 c c . r r AD8426 + v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s r g c d 10nf c c 1nf c c 1nf 4.02k ? 4.02k ? 09490-008 figure 13. rfi suppression c d affects the differential signal, and c c affects the common- mode signal. values of r and c c should be chosen to minimize rfi. any mismatch between the r c c at the positive input and the r c c at the negative input degrades the cmrr of the AD8426 . by using a value of c d one order of magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved.
preliminary technical data AD8426 rev. prd | page 15 of 20 applications information differential drive figure 14 shows how to configure the AD8426 for differential output. +in ?in ref AD8426 v bias r + ? op amp +out ?out r recommended op amps: ad8515, ad8641, ad820. recommended r values: 5k ? to 20k ? . 09490-009 figure 14. differential output using an op amp the differential output is set by the following equation: v diff_out = v out+ ? v out? = gain ( v in+ ? v in? ) the common-mode output is set by the following equation: v cm_out = ( v out+ ? v out? )/2 = v bias the advantage of this circuit is that the dc differential accuracy depends on the AD8426 and not on the op amp or the resistors. this circuit takes advantage of the precise control that the AD8426 has of its output voltage relative to the reference voltage. op amp dc performance and resistor matching do affect the dc common- mode output accuracy. however, because common-mode errors are likely to be rejected by the next device in the signal chain, these errors typically have little effect on overall system accuracy. tips for best differential output performance for best ac performance, an op amp with at least 2 mhz gain bandwidth and 1 v/s slew rate is recommended. good choices for op amps are the ad8641 , ad8515 , or ad820 . keep trace lengths from resistors to the inverting terminal of the op amp as short as possible. excessive capacitance at this node can cause the circuit to be unstable. if capacitance cannot be avoided, use lower value resistors. for best linearity and ac performance, a minimum positive supply voltage (+v s ) is required. table 9 shows the minimum supply voltage required for optimum performance where v cm_max indicates the maximum common-mode voltage expected at the input of the AD8426 . table 9. minimum positive supply voltage temperature equation less than ?10c +v s > (v cm_max + v bias )/2 + 1.4 v ?10c to +25c +v s > (v cm_max + v bias )/2 + 1.25 v more than +25c +v s > (v cm_max + v bias )/2 + 1.1 v
AD8426 preliminary technical data rev. prd | page 16 of 20 precision strain gage the low offset and high cmrr over frequency of the AD8426 make it an excellent candidate for bridge measurements. the bridge can be connected directly to the inputs of the amplifier (see figure 15). 5 v 2.5v 10f 0.1f AD8426 +in ?in r g 350 ? 350 ? 350 ? 350 ? + ? 09490-010 figure 15. precision strain gage driving an adc figure 16 shows several different methods of driving an adc. the adc in the aduc7026 microcontroller was chosen for this example because it has an unbuffered, charge sampling architecture that is typical of most modern adcs. this type of architecture typically requires an rc buffer stage between the adc and the amplifier to work correctly. option 1 shows the minimum configuration required to drive a charge sampling adc. the capacitor provides charge to the adc sampling capacitor, and the resistor shields the AD8426 from the capacitance. to keep the AD8426 stable, the rc time constant of the resistor and capacitor needs to stay above 5 s. this circuit is mainly useful for lower frequency signals. option 2 shows a circuit for driving higher frequency signals. it uses a precision op amp ( ad8616 ) with relatively high band- width and output drive. this amplifier can drive a resistor and capacitor with a much higher time constant and is, therefore, suited for higher frequency applications. option 3 is useful for applications where the AD8426 needs to run off a large voltage supply, but drives a single supply adc. in normal operation, the AD8426 output stays within the adc range, and the ad8616 simply buffers it. however, in a fault condition, the output of the AD8426 may go outside the supply range of both the ad8616 and the adc. this is not an issue in this circuit, because the 10 k resistor between the two amplifiers limits the current into the ad8616 to a safe level. AD8426 ref 100nf 100 ? 10k ? 10 ? 10nf adc0 adc1 adc2 agnd 3.3v 3.3v 3.3v option 1: driving low frequency signals option 2: driving high frequency signals option 3: protecting adc from large voltages 3.3v AD8426 ad8616 aduc7026 ref 3.3v 10 ? 10nf AD8426 ad8616 ref +15v ?15v av dd 09490-065 figure 16. driving an adc
preliminary technical data AD8426 rev. prd | page 17 of 20 outline dimensions compliant to jedec standards mo-263-vbbc 062309-b 3.75 bcs sq 4.00 bsc sq 0.65 bsc 0.75 0.60 0.50 top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator coplanarity 0.08 1.00 0.85 0.80 0.35 0.30 0.25 0.05 max 0.02 nom 0.20 ref bottom view 0.60 m a x 0.60 max 1.95 ref sq 1 16 5 8 9 12 13 4 figure 17. 16-lead lead frame chips scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad, with hidden paddle (cp-16-19) dimensions shown in millimeters
AD8426 preliminary technical data rev. prd | page 18 of 20 notes
preliminary technical data AD8426 rev. prd | page 19 of 20 notes
AD8426 preliminary technical data rev. prd | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr09490-0-6/11(prd)

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